Summit Attends 2017 IPC Reliability Forum

IPC continues to lead our industry by example with their inaugural Reliability Forum, held in Chicago in April. The event was focused on manufacturing high-performance products and featured industry royalty from both a speaker and audience standpoint.

Event Background

The event steering committee charged with developing the forum was headed by Program Chair Michael Carano, and included Don Dupriest, Michael Jawitz, Craig Hillman, Gary Ferrari, Jack Fisher, Denny Fritz, and Sanjay Huprikar, VP of the IPC Member Services. Mike Carano, VP of RPB Chemical Technologies served as the forum’s ringleader, host and emcee. I was fortunate enough to have been asked to participate and speak at the event, and I feel an obligation to let those who were not able to attend this year know what an invaluable educational opportunity this ongoing forum presents for our industry moving forward.

The Audience

The forum was extremely well attended, with  a  veritable  who’s  who  of  our industry’s supply chain, including raw material and equipment suppliers, PCB fabricators, contract manufacturers and OEMs. Companies represented included: Amphenol, Atotech, Aurora Circuits, CTS, DfR Solutions, Dow Chemical, Dow Electronic Material, DuPont–RTP, Embraer S.A., Extreme Engineering Solutions, FTG Circuits, HDP User Group International, Holaday Circuits, Intrinsiq Materials, Inventec Performance Chemicals, IPC, KEMET Electronics, Lockheed Martin Space Systems, Lockheed Missiles and Fire Control, MacDermid Enthone, MEDEL, Minco, Motorola, Nexteer Automotive, Northrop Grumman, NSWC Crane, NTS, Orbital, Park Electrochemical, Penn State University, Precision Analytical Laboratory, Prismview, Raytheon, RBP Chemical Technology, Rockwell Collins, Rolls- Royce, SAIC, Summit Interconnect, The Right Approach Consulting, ThingWeaver Solutions, TTM Technologies, Ventec, and ZESTRON.

The Topics

The Steering Committee did a wonderful job of assembling a lineup of topics that were both relevant to the forum’s theme of manufacturing high-performance products, and presenting insight from our industry’s brightest technological minds. What follows is a brief high- light of each speaker’s presentation.

Keynote Presentation: What Makes our Organization a Global Leader

Phil Titterton, President of the Aerospace & Defense/Specialty Business Unit with TTM, presented tools, techniques and lessons learned on what it takes to be a successful PCB fabricator in today’s global environment. Phil discussed the importance of DFM and its impact on reliability and the need to share best practices with-   in our industry. Phil’s advice to “park the ego at the door” was particularly telling as he explained that collective minds versus islands is critical to solving discrete problems and stream- lining processes. This really resonated with me as some companies still believe that the key to success is to protect their trade secrets. There really are very little secrets; the key to success is in the execution!

Building Reliability In: Design for Reliability

FTG Director of Technical Support Gary Ferrari presented on a variety of issues that affect reliability, such as life cycle development and the considerations of materials, construction, failure modes, and the effects of surface finish and via fill materials on reliability. One of Gary’s key takeaways was that performance may equal reliability, but reliability absolutely equals performance. Gary presented a four-step process in life cycle development of: 1) Identify reliability requirements; 2) Identify life environment; 3) Identify storage environments; and

  • Analyze and selection of components, materials, processes and strategies. A key portion of his presentation dealt with typical microvia failure modes and how to avoid
Generic Protocols for Capture and Transfer of Design Data with IPC-2581

Gary Carter, principal of ThingWeaver Solutions, presented on the importance of collaboration in product development between all interested parties in the supply chain. Gary highlighted the perils of relying solely on Gerber data and focused on the need to employ intelligent data transfer to improve efficiency and quality in PCB design, fabrication and manufacturing assembly. He presented case study results and the “Smart PCB Digital Factory” solution that seeks to remove inefficiencies that exist across electronics design, fabrication, and test processes by replacing the “shopping cart” of engineering files with IPC- 2581B.

Reliable Use of Embedded Passives

Jimmy Baccam, senior electromechanical designer for Lockheed Martin, educated us on what embedded planar capacitance is and is not, along with the pros and cons of this technology. Jimmy continued with lessons learned from fabricating with thin dielectrics, thermal stress and shock testing. A great deal of technical information was shared on the benefits of “being thin” and understanding power distribution.

How Fabrication Affects Reliability— Flowing Reliability from Design to Fabrication & Targeting a Precise Defect with Data:  Reliability  Report  on  WRAP for  Plated Through-Holes

Hardeep Heer, VP and CTO with FTG, presented on two topics impacting PCB reliability, the first focusing on the relationship be- tween design and fabrication. Hardeep began with a review of the current acceptability standards across all market sectors, including life cycle expectations and failure rates. He discussed reliability testing, including thermal cycling and IST testing along with the associated results and data that can be achieved. A particularly informative section was his review of typical PCB failures and the processes and materials that impact reliability. Hardeep’s second presentation discussed WRAP plating, which is defined as “the electrolytic hole plating deposition continuously extending onto the surface from a plated via structure.” Hardeep presented the strategy of a joint DoE between FTG and PWB Interconnect to study the failure modes on WRAP plating. The schedule is to complete the DoE later this year and present the results to the industry at the 2018 IPC APEX EXPO conference.

Military Requirements for Reliability

IPC Hall of Famer Dennis Fritz and Jeff Harms, Reliability & Maintainability Engineering with the Naval Surface Warfare Center, were up next. They presented an overview of military requirements that have an impact on product reliability, with a focus on environmental conditions. They reviewed the requirements of the military standards SD-15, Performance Specification Guide and MIL-STD- 810, Department  of Defense Test Method Standard. Several test methods were reviewed that are used to evaluate a product’s capability to withstand environmental exposure, and concluded by providing a list of resources available to military contractors and suppliers.

Collision of Quality and Reliability Requirements 

Dennis Fritz reviewed a thought-provoking presentation on the synergy between quality and reliability, and the impact on both related to design. Dennis presented a couple of key definitions as it relates to this interaction:

  • Reliability: the ability to function as expect- ed, under the expected operating conditions, for an expected period, without exceeding expected failure
  • Quality: the ability to produce the product, in the manner specified by the customer in the documentation package provided, including any test or legal

A review of the traditional evaluation methods was discussed, followed by an examination of both the strengths and shortcomings of traditional methods. Dennis discussed the reliability challenges of today’s technology, including component miniaturization, additional assembly thermal cycles, lead-free temperature requirements, and the increased stresses placed on laminates. He concluded that while traditional PWB quality measurements are still necessary to keep fabrication processes in control, development of new measurements is needed to assure reliability of advanced technology.

Physics  of Failure

Craig Hillman, Ph.D., CEO and managing partner of DfR Solutions, presented a briefing on the IPC committee work regarding the need to develop modeling and simulations for physics of failure (PoF) requirements. Craig cited in- creasing interest from OEMs is driving the supply chain to perform these type of analyses, and the industry has a general lack of data in these areas. Craig defined the scope of the problem when he stated, “When product volumes easily run into the millions of units, even a 0.1% failure rate problem is a large issue.” An interesting point was made when he presented the reasons that OEMs “hate” environmental testing, including: it takes too long, costs too much, is too late in the process, suppliers rarely fail their own testing, failures are not always relevant, and there is significant disagreement over what failure means.

The scope of the committee work is to identify best practices in the practical implementation of requirements for physics of failure analysis from  the  electronics  supply  chain,  with  a specific focus on component and assembly technology. Craig shared comments from a major PCB fabricator, who stated, “New, upfront methods of modeling must be developed and implemented to increase the ability to quickly discover and correct issues in designs to avoid latent field issues, reduce warranty costs, and increase customer satisfaction.” The goal of the committee is to review the current 20+ standards and leverage the appropriate attributes to develop a new standard to meet the existing expectations of the industry.

Voids in QFN Solder Joints: What should we use for maximum void criteria?

Dave Hillman, principal materials and process engineer with Rockwell Collins, present- ed on the impact of voids in solder joint reli- ability. Dave began with a review of packaging trends, including cost, low profile, electrical performance and thermal dissipation. He then moved on to reviewing the design impacts on solder joint performance, including assembly influences such as solder paste choice and reflow profile. A frank discussion followed regarding the “functionally vague” guidance on acceptable voiding, and the decision to develop a new acceptability criteria that is based on industry data leveraging the work done by the NASA DoD Consortia Team. Dave reviewed the test vehicle and components, thermal profile and testing protocol that was developed and results of the reliability tests performed. The conclusion reached from the data was interesting, with the suggestion that solder joint reliability isn’t the problem, but rather component functional integrity. Dave concluded by stating that the solution is an emphasis on component selection and producibility addressing the function requirements of either thermal transfer or electrical ground characteristics.

Industry Consortium Work: How Collaborative Projects Help Your Organization

Jack Fisher, project facilitator of the High- Density Packaging User Group (HDPUG) presented next on a Collaborative Approach to Reliability Assessment. HDPUG is a project oriented industry consortium addressing the integration of new electronics component packaging and interconnect technologies into member company supply chains. Their mission is to drive innovations in the electronics industry, with over 50 electronics industry companies participating in the group. Jack reviewed the status of a couple current projects: Multiple Laminations, led by Ivan Straznicky of Curtiss-Wright, and the Optical Interface Phase II Project, led by Brice Achkir of Cisco, and M. Immonen with TTM. Jack concluded with the results of the recently closed Electro-Chemical Migration project, led by Mike Bixenman of KYZEN Corp. Significant data, information and results were shared on each of the  projects.

Mitigation of Pure Tin Risk by Tin-Lead SMT

David Pinsky, senior fellow with Raytheon Company reviewed the results of an industry round-robin study on components with pure tin finished terminations that are at risk for tin whisker growth and potential unreliability. The goal of the study was to evaluate the conditions under which typical SMT components will achieve self-mitigation, and a DoE was developed. Many potential factors for consideration were considered for inclusion in the study, and the four factors that were selected were 1) Component packages (16 P/Ns); 2) Board finish (OSP & SNPb HASL); 3) Pad size; and 4) Manufacturing processes. David reviewed the DoE specifics, data and results, including the results of new boards (6−13 months old) and older boards (>5 years old). David presented the conclusions of the DoE, which included 1) Undersides of leads will be mitigated more often than upper sides of leads; 2) Opportunities exist for enhancing self-mitigation through process adjustments; 3) Parts outside of normal shelf life cannot be assumed to self-mitigate in the same manner as parts within normal shelf life.

ENEPIG—Impact of Surface Finishes and No-clean Fluxes

Bill Fox, materials and process assoc. engineer with Lockheed Martin Company present- ed on the reliability of ENEPIG in small solder joints. The premise of Bill’s discussion was that HDI drives finer features on the printed board, and as solder joints become smaller, HASL be- comes problematic. Electroless Nickel/Electro- less Palladium/Immersion Gold (ENEPIG) is a surface finish that has been demonstrated to have a variety of benefits, however, there are concerns that palladium above a certain thickness or content has an adverse effect on the solder joint. Bill reviewed the specifics and results of a number of experimental procedures that were developed to test for a number of conditions. The conclusions noted were 1) No noticeable extent of PdSn4 intermetallics in joints due to the lower Pd thickness of the ENEPIG specifi- cation; 2) Solder joints on ENEPIG demonstrated good shear strength and comparable thermal cycling survivability to HASL; and 3) Pd content from a standard ENEPIG finish is acceptable for high reliability in small solder joints (1.5−2.5 mil). Bill ended by calling for additional discussions on two points: 1) Material and process details such as gold thickness, solder mask thickness, and solder volume are critical factors to very small solder joints, and 2) Gold at 3% in a solder joint may have been a factor in crack initiation, but thermal cycle failures are in the bulk solder joint.

It’s Time to Improve Component Standards  and Measurement

Joe Russeau, president of Precision Analytical Laboratory, asked the rhetorical question “should the industry care about component cleanliness?” and presented the results of  a study by the ad hoc Cleanliness Team. The team member companies included IEC Electronics, Corfin Industries, Secure Components and Precision Analytical Laboratory, and focused on understanding the impact of component cleanliness on reliability. The team has completed the first two of the four phases of the study: Phase I—Printed Circuit Board (PCB) Cleanliness; Phase II—Component Cleanliness; Phase III—Printed Circuit Board Assembly (PCBA) Cleanliness; Phase IV—Reliability Cleanliness Limits.

Joe’s call to action was to continue the dialog in the industry on the following  topics:

  • It’s time to improve component cleanliness standards and measurement
    • Start the discussion (Why should industry care?)
    • What is meant by “cleanliness”?
  • What are the current industry techniques used for measuring ionic “cleanliness”? Resistivity of Solvent Extract (R.O.S.E)
    • Ion Chromatography
    • GEIA-STD-0006, Requirements for Using Robotic Hot Solder Dip to Replace the Finish on Electronic Piece Parts
    • Data Comparison Study (R.O.S.E. vs. IC)
  • Where do we go from here?
Fresh Perspective on Test

William Graver, senior analyst with National Technical Systems (formerly Trace Laboratories), presented the thought-provoking question, “Is test an unnecessary evil, or a life-saving necessity?” William walked through a number of major reliability concerns in today’s environment, and presented some graphic examples of catastrophic reliability failures. Two major failure modes were reviewed in the form of case studies. The first study was on via-pad separation in rigid-flex PCBs, which exhibited a 25% failure rate after two assembly thermal excursions. This was attributed to microetch chemical type, and size of the micro-via. The second study was on plating separation, which also had high failure rates after two assembly reflow cycles. The solutions to this issue were to replace button plating with pattern plate, and to use a thicker wrap plate per IPC Class 3. William concluded by reviewing methods for testing to eliminate failure mode:Figure 10: Yours truly presenting.

  • 5X reflow simulation
  • Interconnect stress testing (IST)
  • New thermal cycle method—CITC
  • -100°C vacuum environment
  • Extra DPA
Inspection: Is it Necessary?

I batted cleanup for the event, and received some feedback the day before from Tony, a quality engineer colleague with one of my clients. After reading the first paragraph of the white paper I sent out as a teaser to the event, Tony told me: “Steve, you are wrong. You can never get rid of all inspection in our business; it just  is not possible.” I said: “You’re right, Tony, but when I send you the entire paper you will see that I am talking about eliminating the profit- sucking practice of using inspection as a Band- Aid to quality problems instead of fixing the process.”

I discussed the point that the customer is paying for our inefficient processes through scrap, rework and returns, and that this knee- jerk reaction has a triple impact on profits:

  1. Inspection by definition is a non- value-add reactive process
  2. It doesn’t address the root cause of the issue and assures it will resurface at some point
  3. Inspection is not effective

The solution is to employ  the  appropriate best-practice tools in your operation, and a number of lean methodologies, tools and techniques were reviewed. The results of a study by Mikel J. Harry, PhD (the father of 6 Sigma) provided food for thought with the audience. Dr. Harry did a benchmark study of U.S. manufacturing companies, and found that that the average sigma level in the U.S. is between 3.5 and 4 sigma. This means that the average company is spending 25% of their revenue on the Cost   of Poor Quality (CoPQ). And remember who   is paying for this: your customers. So, no matter how good you think (or tell your customers) you are, there is plenty of room for improvement. I ended with a remarkable stat:

Foolishly trying to “inspect in quality” by sorting has a greater impact on profit than:

  • Raising prices on your product
  • Hammering your suppliers for lower costs
  • Most any other traditional profit enhancement initiatives
Conclusion

These types of events are sorely needed in our industry, and critical for us to remain at the forefront of technology to support our customers. I look forward to seeing the Reliability Forum gaining momentum as it becomes an annual must attend industry event. I’ll close with a quote from the forum’s driving force, Sanjay Huprikar, when I asked Sanjay about the motivation for developing this event:

“There is a real urgency in the electronics industry to put practical methodologies in place to improve reliability and this year’s IPC Reli- ability Forum focused on processes and mate- rials for long-term reliability. From the keynote presentation that provided an insider’s perspective on the how product reliability is important for good business to the presentations on de- sign for reliability, collision of quality and re- liability requirements, the physics of failure, military requirements for reliability, and more, the event provided attendees with new strategies they were able to take back and implement right away.”   PCB 

by: Steve Williams – I-Connect007 – Review of the 2017 IPC Reliability Forum

 

The PCB Magazine • July 2017

Leave a Comment